I am deeply motivated to acquire knowledge and continuously refine my skills to become highly proficient in the semiconductor industry.
Analog circuit design: RF circuits, Oscillators, PLLs, Op-amps, Energy-harvesting.
Digital circuit design: Adders, Multiplexers, Registers, DRAM, SRAM.
Layout design: Area optimization, Design automation, Open source design.
System design: Scan chain insertion, Systems-on-Chips.
HDL: Verilog, Systemverilog.
RTL: Front-End design, synthesis, verification.
FPGA: Embedded systems, DSP applications, Neuromorphic computation.
Medical Devices, Ultrasound/terahertz Devices, EAD Tools
This paper presents a low-power, and energy-efficient pass transistor-based full adder, along with two other approximate adders sharing the same constructional pattern. Initially, three conventional full adders are analyzed, namely the mirror adder, XOR and XNOR-based adder circuits. Based on these circuits, a new energy-efficient 12T full adder is designed that consumes much less power compared to conventional full adder circuits. The design is implemented in 45nm technology with a +0.8 V supply voltage. Schematic simulations in Cadence Virtuoso tools showed a 60%-85% improvement in power consumption compared to previously stated conventional adders. Furthermore, the research extends to the development of two innovative approximate adder designs that demonstrate remarkable improvements in power efficiency while maintaining an acceptable level of accuracy. Finally, a comparative analysis of conventional approximate full adders proved our proposed approximate adders outperformed existing ones, in terms of power consumption, power delay product, and bit error rate.
This paper presents dual control voltage in the conventional 5-stage current-starved ring voltage-controlled oscillator (CSR-VCO) to provide a wider tuning range and fine-tuning possibilities for radio frequency (RF) applications. The circuit is implemented in 45nm CMOS 1V process technology. The proposed circuit is found to have an oscillation frequency range from 6.51GHz to 13.66GHz for the first control voltage (0.8V-1.8V). On the other hand, the second control voltage (1V-1.8V) demonstrates a better linear frequency range, spanning from 5.65GHz to 13.66GHz when the first control voltage is fixed at 1.8V. Modifying the first control voltage, in conjunction with the second, results in precise changes in the frequency level, providing the potential for fine-tuning in radio frequency applications. The 1MHz offset phase noise of the VCO at the maximum output frequency of 13.66GHz is found to be -75.96dBc/Hz and the corresponding power consumption is found to be 2.68mW.
This study delves into the realm of approximate adders, strategically navigating the delicate balance between precision and efficiency in high-performance, energy-efficient digital technology. Within this context, we introduce three novel approximate adder architectures that yield substantial reductions in power consumption, heightened computational efficiency, and a streamlined circuit complexity when compared to their accurate counterparts. Employing 45nm technology with a +0.8 V supply voltage, our proposed Efficient Approximate Adders (EFAAs) showcase superior performance metrics, boasting a noteworthy edge in power-delay product (PDP) and bit error rate (BER) compared to existing approximate adders. The reported PDP values consistently fall within the range of 4 to 5.5 (×10-5), while the BER remains within a safe threshold. Noteworthy is our acknowledgment of potential accuracy loss and the intricacies associated with error correction, especially in the context of digital signal processing (DSP) applications.
The Internet of Things (IoT) paradigm and cloud-based computing with microcontrollers play an important role in future smart grids. In an electrical grid system, implementing the concept of economic dispatch and merit order of generators can minimize the total generating cost of the power plants. In this project, we propose an IoT-based microcontroller computing framework to maintain the merit order of generators based on the consumers’ demand. The proposed design is formulated by using the ESP8266 microcontroller and a current sensor module (ACS712) to make real-time decisions about which power plant needs to shut down in time for the best economic dispatch and which area has to be under load shedding. The current sensor measures the load consumption rate and sends the data to the microcontroller. By the amount of supply needed and considering the generation costs of different types of power plant, the microcontroller computes and provide a decision on the merit order of generation. In addition, the microcontroller sends the decision of area-wise load shedding based on the priority of consumers. The Wi-Fi system allows the microcontroller to send all the information to a load dispatch centre to take the necessary steps. The main benefit of the proposed project is that it effectively reduces the generating cost of the power plant and it might helps the load dispatch centre to create a model to take decisions on load dispatching.
Optimizing Voltage Controlled Oscillators (VCO) in PLL circuit.
Developing hardware based approximate computation circuit to introduce in RNN/LSTM model.